EDA Confidential ___________________________________________________________ DAC 2010: House of Glues by Peggy Aycinena ___________________________________________________________ July 12, 2010   For many people, going to DAC is like going to a High School Reunion. There are many familiar faces you can't quite put a name to, and other faces belonging to perfect strangers who call you by name and seem to know who you are. Of course, there are also lots of good friends at DAC whose names and faces you do remember – and that's the best! The other reason DAC's like a High School Reunion? Every year, the population seems to get older, with more people in the "Aging Demographic" bucket. But, I digress ... ************************************ House of Glues ... Although the 2010 Denali Cadence Party was held at the House of Blues on June 14th at this year's Design Automation Conference in Anaheim, DAC 2010 wasn't really about The Blues. Instead, #47DAC was about The Glues – the glues that bind the ecosystem together, including those who ... * Develop the EDA Tools * Provide the IP * Design the Hardware, Packages & Boards * Develop the Software * Run the Foundries * Do the Test and Packaging * Integrate the Software * Assemble the System * Manage the Product Launch, Distribution & Product Life Cycle * Sniff out the next Market Opportunity & Translate it into Product Specs * Handle the PR & Marketing * Teach at the Universities * Learn at the Universities * Manage the Show It's a complex multi-node network (not nearly as neatly segmented as this list would imply), all held together by a messy collection of glues. And this year in Anaheim at #47DAC, the majority the talk was about those glues ... The Good Glues – promoting cooperation, collaboration, partnering, and innovation – that loosely (or more firmly) bind together a host of different nodes in the multi-node network, and ... The Bad Glues – harder to detect and never openly acknowledged – that say if you're living at one node in the multi-node network, you've got to stay there forever. You're never going to be allowed to change because: a) People who come to DAC don't really like change, and b) People say they've already staked a claim to that node, and you are NOT welcome. Another way of describing The Bad Glues? They're on par with the gum you get on your shoe at the parking lot in the grocery store. Somebody else put the gum there, and now it's your problem to deal with. Which brings us to John Bruggeman and EDA360, and not necessarily in that order. Bruggeman & Co. are trying to change Cadence into something else (not the first time, of course, this conjuring trick's been tried at good'ol CDNS), but the industry's saying: Raspberries to you, Bruggeman. Cadence has to be what it's always been, and you're not allowed to change that. And EDA360? Nothing new there either, Bruggeman. We'd already thought of all of that and you can't own it. No matter how much bravado & brimstone you throw at it. But again, I digress ... ************************************ Sunday: June 13th ... Although the Design Automation Conference officially opened on Monday, June 14th, things really got underway on Sunday evening with the annual EDAC Reception and Gary Smith on EDA Industry Update taking place in quick succession at the Hilton Hotel next to the Anaheim Convention Center. There were hundreds of people on hand for both events in adjoining ballrooms, plenty of food, wine, beer, and conviviality. There were also a lot of ideas and themes being bandied about amidst the many people in attendance, and public & off-the-record snips and snaps from people well lubricated and nervous/agitated about the potential for success/ROI/failure over the next several days. Here’s a brief Editor’s Notebook list of just a few of them ... * Thanks to the efforts of Jasper CEO and EDAC Board Member Kathryn Kranen – for the first time ever, the Sunday Night Reception was sponsored by 5 key EDA customers: Qualcomm, Intel, ARM, NVIDIA, and STMicro. Per Kranen, these customers were delighted to show their long-standing appreciation to the EDA industry for the tools that make what they do possible. * Ironically, a hot topic on Sunday evening included getting Full Value for EDA tools, as in Will we ever???  Between customer demands and pricing pressures from fellow vendors, EDA tools continue to be significantly under-priced and under-appreciated, according to many long-time observers. * Discussion continued as to whether IP or EDA will be the growth sector going forward, with many believing that EDA will continue to grow slowly, as has been the case for a number of years now, while IP will only gain additional momentum. * Exhibitors continued to worry that attendance at conferences like DAC is in a steady decline. Other exhibitors argued that the way to guarantee the ROI on marketing venues like DAC is to arrange for customer meetings before the show – and to staff the booth accordingly. * Spoiler Alert: Skipping to the end of the week in Anaheim, here are the official numbers for #47DAC, and #46DAC for comparison ... DAC 2010 Anaheim Stats:    Full Conference = 1,554    Exhibit Attendees = 3,444    Exhibitors, Visitors & Guests = 2,557    Total = 6,001    [sketchy math in Press Release?] DAC 2009 San Francisco Stats:    Conference Attendees = 1,962    Exhibit-only Attendees = 3,337    Booth Staff = 2,697    Total = 7,996 * The Press Room versus Blog-o-Sphere continued to be a source of amusement, with those who cover the industry having rights to one venue or the other, but not both [per an email I received prior to DAC]. Meanwhile, rumors had it that JCooley complained Sunday afternoon that the food in the Press Room was woefully inadequate. * Gary Smith commended Mentor’s Wally Rhines and Synopsys’ Tom Williams for having brought additional industry attention over the last several years to the emerging importance of 3D Design and TSVs [Through Silicon Vias]. * Mary Olsson from Gary Smith on EDA said current growth potential in 3D TSVs is comparable to the rapid growth seen in an earlier era with surface mount technology. * Mentor CEO Wally Rhines noted that Calibre already supports features needed for realizing 3D TSVs, and at no additional cost. * Gary Smith said the highest revenues in EDA are earned by selling tools to the Power Users – those doing cutting edge designs. However, those cutting edge designs are actually less expensive, from a design point of view, for exactly the reason that excellent tools are used to do those designs. At the same time, Smith noted that Cadence, having solved the "Mike" problem, is now playing catch-up to Synopsys in the Power User market – and may succeed eventually. * Gary Smith said he spent time in late 2009 scanning the Open Source Software Landscape in hopes of finding apps that support parallel programming, but his search came up short. Nothing’s going on there, Smith said. * Finally, the evening's festivities were enlivened by an impromptu Hawaiian Shirt Contest, contenders being Yatin Trivedi and Gabe Moretti. Moretti didn't get the memo that Bermuda Shorts were also required, so lost out to Trivedi. ************************************ Monday: June 14th ... DAC 2010 officially opened Monday morning with the show floor primed and ready to go. Lots of people poured in to enjoy Free Exhibits Monday. Happily, many of them rushed right over to the Pavilion Panel Stage where EDA Zydeco had its debut. With EDAC's Bob Gardner on tenor sax, Xilinx' Mike Santarini on electric guitar, EDA Confidential's Peggy Aycinena on Belsono accordion, and Gary Smith providing vocals and washboard, it was an eyeful and earful all rolled into one [available here on YouTube]. Our 3-minute rendition of Uncle Bud complete [if you blinked, you missed it], Gary Smith launched into his annual 45-minute State of the EDA Nation Address, with many of the several hundred in the audience no doubt hoping that their company and/or tools would be mentioned in Smith’s prediction of where the industry is going and how it’s going to get there. For the record, I actually find these kinds of lists, also published in ESNUG, to be counter-productive. Naturally, companies love to find their names there and always issue Press Releases announcing same, but there are plenty of valuable offerings from companies who don't have the PR Apparatchiks in place to guarantee inclusion. Having said that, here’s the complete list of companies included in Smith’s "What to See at DAC" ... * Forte's integration of the recently acquired Arthmatica libraries * Cadence's C-to-Silicon ESL synthesis * Oasys as one of the key components of the silicon virtual prototype * Mentor's Vista for ESL * Apache & DOCEA Power for ESL power analysis * Bluespec for software virtual prototyping * Synopsys for recent software virtual prototype acquisitions * Atrenta, Zocalo and NextOp for functional verification advances * Gate Rocket for debug * GiDEL for rapid prototyping * SpringSoft, described as the "King of Debug" via Laker * Silicon Frontline and Micrologic for 32-nanometer extraction * Solido for custom design offerings * Sapient & IC Manage for interoperability tools * Tuscany for enterprise tools * Magma, which Smith described as “almost” an analog company Smith also revisited the slides from his Sunday Night presentation and concluded: The industry needs major innovations in Software Design tools and Methodologies to keep Moore’s Law on track. Then, per Smith, by the end of the decade we'll begin to see the the switch to a new silicon, or non-silicon, design fabric. Following Smith's presentation, it was off to Conversation Central in the Synopsys Booth for a one-on-one radio chat with Podcaster & EDA Veteran Ron Ploof. It was a blast to be ‘On the Air’ with Ploof, discussing the origins of EDA Confidential, why RSS feeds would drive Acoustic EDA podcasts to a wider audience, the charm of Open Source, and what it means when someone says something is off the record. Ron Ploof's best advice with regards to giving away content for free ... * Obscurity is more to be feared than people stealing your content! [Editor's Note: My BlogTalkRadio Interview was only the first of many in Synopsys' Conversation Central at #47DAC. For the complete list, Click Here.] After my visit with Ron Ploof, it was off to the Workshop for Women in Electronic Design on the 2nd floor of the Convention Center. Under the inspired leadership of Oracle’s Pam Parrish and Jasper’s Holly Stump, the event was free thanks to the many sponsors: Atrenta, Axiom, ClioSoft, EVE, Jasper, Mentor Graphics, Real Intent, SpringSoft, Synopsys, ACM, CEDA, and EDAC. The lunchtime keynote delivered by Azzarello Group CEO Patty Azzarello offered dynamic advice to anyone hoping to wrest control of their day-to-day jobs, their career aspirations, and their reputations for accomplishment. Major take-aways from Azzarello's talk ... * Doing everything that's asked of you at work may seem like the right thing to do to get ahead, but it may only end up positioning you as a valuable droid, lacking leadership skills. * If you want to be successful, schedule a solid 2 hours per week of alone time where you can think through upcoming projects, and contemplate developments in your career and work-related agendas. * Delegate and work with the team. Successful people do not succeed alone! * Be brave! Leave your comfort zone! Attempt the daring deed! * Deliver excellent results and make sure people know which contributions are yours: Brag on your successes! Following the keynote, 3 additional speakers offered career advice: Real Intent VP of Sales Carol Hallett, SunLabs/Oracle Principal Engineer Gilda Garreton, and Jasper CEO Kathryn Kranen. Per Kranen ... * Whether you're an AE or a developer, always link your work to your end-customer's success. And, always demand the highest compensation for your contributions to the enterprise! WWED 2010 culminated with the presentation by #47DAC General Chair Sachin Sapatnekar of the 2010 Marie R. Pistilli award to Magma VP Mar Hershenson. Hershenson gave a moving acceptance speech honoring her parents, her husband and children, her grad school colleagues and advisors, those who invested in Sabio Labs [acquired by Magma in 2008], and Magma CEO Rajeev Madhavan, described by Hershenson as a great and diligent problem solver. Best line of Hershenson's speech... * My mother always said being a woman is no excuse for accomplishing less! After WWED 2010, it was back to the Exhibition Hall, lively with the heaviest 1-day attendance in Anaheim. Over in Conversation Central, ARM's Lori Kate Smith was interviewing Mike Santarini, who argued that journalists and bloggers should protect their credibility by practicing full disclosure as to their employers and/or other affiliations. If that knowledge is available up front, Santarini said, even those who work for vendor companies can offer up extremely valuable points of view. Next, it was back to the Pavilion Panel Stage for my one-on-one interview with Mar Hershenson. In the course of our 45-minute conversation, we discussed Hershenson's career, her opinions on VC-funded startups versus those that are bootstrapped [she prefers the latter], whether grad students should work in conventional enterprises before launching into a startup [she advises the former], and careers in academia versus industry. Hershenson said there are no simple answers to any of these choices – each individual has to find their own way – but anyone who thinks professors have an easy life, should think again. The Academic is as stressed as the Industry Worker Bee. From the Pavilion Panel, it was off to the Bluespec Booth for a great chat with Marketing VP George Harper. The company has just released Bluespec 2.0, entering new areas of the design flow at the system level. Harper's very bullish on his company and believes the industry will be taking a closer look at their offerings in the move to higher levels of abstraction. Suddenly, it was time to run to the front of the Convention Center to catch the 6 PM bus to Disneyland, courtesy of Mentor Graphics. A crowd of 150+ were on hand for the company's annual Analyst/Press/Customer Wallapalooza! A sumptuous dinner at Studio 17 in California Adventure was served up complete with a rousing on-stage stump speech from Mentor CEO Wally Rhines, who works a crowd as well as any politician. Rhines got a boisterous round of applause for his comments, and noted – thanks to a shout-out from Gary Smith – that Mentor is now Number 2 in EDA in terms of tool sales. Rhines said the industry should watch closely as Mentor makes a move to become Number 1. More boisterous applause ... After dinner, we were efficiently herded over to Disneyland, through 500K tourists on Main Street, and on into Carnation Plaza, where the Happy Guests of Mentor had special, crowd-free seating in the Happiest Place on Earth, complete with a view out to Sleeping Beauty's Castle and the 9:30 PM Fireworks Extravaganza. Congrats to the Mentor Team for a spectacular evening! Following the fireworks, everyone was excused to either head back to their hotels or walk to the nearby House of Blues for what was rumored to be the last Denali Party – the Denali Finale! – thanks to the recent Cadence acquisition. [Editor's Note: Although I was not at the party myself, I did get a colorful report from Cadence CMO John Bruggeman the next afternoon during a meeting that included Corporate Communications VP Lynne Cox. Bruggeman said he stood on stage at the Denali Cadence Party and promised the surging crowds that this iconic celebration of Life & All things EDA would go on for not just 1, not just 5, but 15 more years!] Of course, the party wasn't the only topic of conversation in Anaheim related to the Denali acqusition. Many discussions at #47DAC were electrified by back-of-the envelope calculations as to out how much Denali Co-founders Sanjay Srivastava and Mark Gogolewski pocketed with the sale of their 15-year-old bootstrapped company. Rumor has it they each held 40% – please note, per rumor ONLY – so given the stated sale price of $315 million less $45 million in cash, Srivastava and Gogolewski each cleared [do math here] a fair chunk of change. ... Definitely the Stuff of EDA Dreams in the Happiest Place on Earth! ************************************ Tuesday: June 15th ... For those who did not attend the Denali Cadence Party, Tuesday morning was easy. Be in Room 203B by 7:30 AM for the Accellera Breakfast celebrating the Universal Verification Methodology [UVM 1.0], released May 17, 2010. Accellera Co-founder Gabe Moretti hosted the morning's discussion, which included reps from Freescale, Intel, Xilinx, Mentor, Synopsys, and Cadence – all of whom were involved in developing the new standard. That cooperative effort notwithstanding, tangible tensions were served up in the crowded room along with the coffee, eggs and sausage. It all started calmly enough, with Moretti commending the countless hours and dedicated professionals that produced UVM 1.0. Xilinx said UVM 1.0 would help fill the need for standardization on Verification IP, and Intel offered a back-handed compliment ... * Convergence on what's good is more valuable than divergence on what's better. Things turned dark, however, when SNPS, CDNS, and MENT began duking it out over issues of backwards compatibility, code bloat due to "everybody trying to stuff in what they want," "stuff getting into the standard without complete evaluation," and the agonies and/or ecstasies of permitting community contributions [read: "Open Source"] to the standard. Finally, any semblance of good cheer left in the room was effectively snuffed out with Mentor's comment ... * When you design a horse by committee, you get a camel! As I tiptoed out of Room 203B, hoping to catch the #47DAC Opening Session upstairs in Ballroom ABC, an embittered audience member was becoming openly hostile: "We just got used to OVM, and now you're shoving UVM down our throats!" Going from Bad Glues to Good at DAC ... Rushing into the back of Ballroom ABC, I found the darkenend, cavernous space filled to the brim with an audience of 600+ for the Opening Session unfolding on the ginormous stage in the distance. The DAC Executive Committee was up there, arrayed in their signature matching shirts, handing out a boat load of awards ... * Corlan McDonald  [P.O. Pistilli Undergrad Scholar] * Ryan Cochran  [Richard Newton Grad Scholar] * Abdullah Nowroz  [Richard Newton Grad Scholar] * Randal Bryant  [2009 Phil Kaufman Award] * Mar Hershenson  [2010 M.R. Pistilli Award] * Andrew Kahng  [IEEE Fellow] * Anand Raghunathan  [IEEE Fellow] * Saeed Namarvar  [IEEE Circuits & Systems Society] * Alfred Dunlop  [CEDA Distinguished Service Award] * Richard Smith  [CEDA Distinguished Service Award] * Giovanni De Micheli  [CEDA Distinguished Service Award] * Matthew Guthaus  [ACM SIGDA Distinguished Service Award] * Alex Jones  [ACM SIGDA Distinguished Service Award] * Diana Marculescu  [ACM SIGDA Distinguished Service Award] * Mary Jane Irwin  [ACM Athena Lecture Award] * Himanshu Jain  [ACM PhD Dissertation Award] * Deming Chen  [SIGDA Outstanding New Faculty Award] * Puneet Gupta  [SIGDA Outstanding New Faculty Award] * Hao Yu  [ACM Transactions on DA 2010 Best Paper] * Joanna Ho  [ACM Transactions on DA 2010 Best Paper] * Lei He  [ACM Transactions on DA 2010 Best Paper] Following the awards, the Opening Keynote was delivered by GlobalFoundries CEO Doug Grose,  an under-stated speaker with an over-stated message. Grose spoke at length about the advantages of cooperation and collaboration with seasoned organizations like GF, which owns Chartered Semiconductor and partners with AMD, to improve cost efficiencies and customer satisfaction. As promising as his scenario sounded, however, Grose's thesis is not new here in 2010 because TSMC has beat GF to the punch, as detailed in "TSMC: The New Pax Romana" ... "All tool and IP vendors will provide solutions that are interoperable, standardized to the standards that TSMC has established and/or approved. Yes, efficiency is the goal, collaborative R&D is the goal, and saving time & resources is the goal. But ultimately, TSMC calling the shots is the real goal!" After his talk, I rushed to the front and got in the first question as Grose came off the stage. Did he think part of the appeal of the GF-IBM-Samsung Common Platform thing is that it's the Not China option? [See "The Un-Common Platform".] Grose was quick to respond: "Absolutely! We can't get into China at all!" [Editor's Note: Grose's was not the last GF voice to be heard at #47DAC. All week long, at practically every session I attended, someone from GF was the first to the mic at the outset of every Q&A, asking questions and making themselves highly visible. After hearing the tone & tenor of those questions, I began to believe Grose's Tuesday morning assertion: GF's mission is all about the people. Nonetheless, rumors of discontent in the worldwide GF organization could be faintly heard, if you put your ear to the ground at the Anaheim Convention Center. Hmmm. What to believe?] Following the keynote, it was back to the Pavilion Panel Stage yet again, this time to hear Vista Venture's Jim Hogan moderate a panel: Nightmares at 22 Nanometers. Panelist Aki Fujimura from D2S said only high-volume chip producers can afford the move to 22 nanometers, hence nightmares involve squelching innovation for the smaller players. Xin Wu from Xilinx said increased mask & lithography costs, more restricted design rules, and problematic layout issues together create the 22-nanometer nightmare. Aaron Thean from Qualcomm said engineers will undoubtedly solve the technical problems at 22 nanometers, so the nightmare's been pushed to the business side of the equation: Given the expense, is there sufficient ROI to justify the move to 22nm? I asked the panelists, why mess around with 22 nanometers at all: Why not go 3D & just go up? The panelists seemed reluctant to answer, but Qualcomm's Riko Radojcic sitting in the audience nearby cheered his approval, while Jim Hogan closed out the panel ... * Yes, 3D is exciting, but that's for next year! Next, it was back upstairs to join an SRO crowd at the 2010 CEDA Luncheon, starring Tabula CEO Steve Teig. You'll want to go online and find the archived video of this hour-long lecture when it becomes available. Some paraphrased highlights ... * Traditional von Neumann compute models will not suffice in today's brave new world of multi-core processing. * It just takes too friggin' long to get an e- from compute location to memory register, and back again. * What to do? Use a "physically aware" non-von Neumann machine with a "causal notion of time" to get higher performance and more power-efficient computing. This isn't all Teig had to say [he also spoke about Alan Turing, and mentioned the Conway-Meade Revolution], but it's enough to explain why: a) Many in the audience were spittin' mad by the end of the hour, claiming that Teig's "new ideas" were just "old ideas" restated; b) Many academics in the audience were totally jazzed: We need MORE of this kind of thing at DAC to shake things up in the industry; and c) Computer Scientists need to step away from their C code! Following the CEDA Lunch, it was a dash downstairs to the Cadence booth for the interview with Bruggeman & Cox mentioned above, that somehow grew from 30 minutes to a full hour, leaving the next journalist in the queue cooling his heels outside for half an hour while Bruggeman and I blathered away. [I saw that journalist later at the Synopsys Dinner and was embarrassed to learn he'd been inconvenienced.] So, what did Bruggeman have to say that was so interesting? Well, it wasn't exactly what he said, as much as how he said it ...  Blunt-ly. In your face-ly. This-is-who-I-am-and-what-the-industry-needs-ly. And his message? We're re-inventing the business model, re-evaluating the supply chain, and dis-intermediating the value chain. We're moving to assist our customers in a new way to develop apps that create phenomenal user experiences. All of this flows into the features and functions of our new products, our relationships, and our M&A activity. Okay, it certainly sounds good, but what does it all mean? Where's the beef? Perhaps only time will tell, but meanwhile ... Bruggeman's generating a lot of interest around his/Cadence's manifesto, EDA360, which somehow articulates a new "vision" for the company. And – given a choice of listening to Steve Teig for an hour, or John Bruggeman – I'd be hard pressed to decide which of these Visionaries is more Visionary. Again, perhaps only time will tell. Moving from current to future visionaries, next it was on to Room 204AB to mingle amidst various students and posters involved in the ACM Student Research Competition, organized by Brown University's Iris Bahar and Carnegie Mellon's Diana Marculescu. Speaking with the various students, as they carefully and enthusiastically explained the intent and results of their research, was perhaps the single most transporting experience at DAC. An example: "Virtualizable and Preemptible HW/SW Runtime Environment for Reconfigurable Computing Systems," presented by Chun-Hsian Huang from Taiwan's National Chung Cheng University. It seemed that Huang should be working with Tabula's Steve Teig, as they're both trying to push FPGA technology to more fully realize the potential. Afternoon shadows were growing long when I arrived next at the Press Room [where there was food!] to meet up with Alban D'Halluin, Director at Tiempo, a company injecting new life into an old, previously dismissed technology – asynchronous design. Per D'Halluin, "Our approach is two-fold. We offer asynchronous IP, packaged together with an interface, so it looks like any clocked block, but with all the benefits of asynchronous design. We also have a fully-automated tool for asynchronous synthesis, and a flow to support custom design for asynchronous systems [based on] standard SystemVerilog. With better performance guaranteed, customers are now exploring how to replace some parts of their chips with asynchronous circuits." Moving from one promising technology to another, Tuesday at DAC wrapped up with the 6 PM MEMS Panel in room 210, moderated by Jim Hogan, which included Coventor's Mike Jamiolkowski and Cadence's Steve Lewis. Coventor and Cadence are "partnering to establish an easy-to-follow MEMS design flow that's fully integrated" into the established analog and mixed-signal design flow. Expect to hear more about the MEMS flow, and Coventor in particular, going forward. Unfortunately, I had to leave before the MEMS discussion ended – already late to the Synopsys Press/Analyst Dinner a few blocks from the Convention Center. When I arrived at the restaurant, the party was in fully swing – ably hosted by Synopsys Worldwide PR Director Yvette Huygen and Synopsys President Chi-Foon Chan – with tables and wine glasses all brimming over with good cheer, which brings me back to the beginning of this epistle ... Those who have enjoyed the warm hospitality of a Synopsys Dinner at DAC know that there are lots of good friends there whose names and faces you do remember – and that's the best. Thanks, Synopsys, the evening was just great! Meanwhile, back at the Hilton Hotel, the 2010 DAC Party was underway, sponsored this year by Denali. Only time will tell if this official, all-attendee party will eventually develop the Legs & Legend associated with the more coveted Denali Cadence Party. ************************************ Wednesday: June 16th ... Day 3 at #47DAC dawned with Anaheim's typical June Gloom mix of fog & smog, but there was no time to contemplate local weather patterns: Synopsys was offering breakfast to 175+ folks plucky enough to arrive at the Marriott Hotel by 7:30 AM for the annual DAC Interoperability Event. Hosted by Chi-Foon Chan, it's clear the man never tires because, despite his hosting duties the previous evening, Dr. Chan brought his A Game to the 3D Frivolities on Wednesday morning. So did the rest of the Synopsys Team, by the looks of things. Chan's panel included speakers from ARM, STMicro, TSMC and GlobalFoundries. I'm sure they all made quotable comments, but I was too busy playing with the 3D glasses that came free with breakfast to note them all. Let's presume, however, that kudos were heaped on the concepts of collaboration, cooperation, and interoperability. What really goes on behind the scenes in the industry as far as these ideals are concerned, however, is anybody's guess. I know I wouldn't want to be an EDA vendor these days, having to decide whether to seamlessly integrate into the TSMC-approved or GF-approved flow. Meanwhile, as is always the case at DAC, I had to leave before the Interop Breakfast was complete, dashing next door to the Convention Center for the 9 AM panel: 3D Stacked Die: Now or the Future?   The room was completely packed, which is only worth noting if you believe that SRO crowds in sessions at DAC indicate state-of-the art or cutting-edge technologies. Jim Hogan may believe the conversation about 3D is for next year, but the 200+ folks in room 207AB on Wednesday morning at DAC didn't get the memo. The discussion, one of the best I attended in Anaheim, was moderated by Apache CEO Andrew Yang, and included Samsung's Myung-Soo Jang, TSMC's LC Lu, imec's Marchel Pol, Qualcomm's Riko Radojcic, and independent consultant Joe Adams. Among the highlights ... * Jang: SoCs and wide I/O memory stacking, along with TSVs, offer a competitive edge over traditional package-on-package SIPs. * Adams:  3D adoption will mimic SIP adoption – will initially be associated with vertically-integrated organizations, and then move to 3rd-party suppliers as the technology matures. However, look for traditional market incumbents to resist 3D by undercutting the market. * Lu:  TSMC is ramping up for 3D manufacturing in 2012. Technical challenges include wafer thinning, bonding with accurate alignment, TSVs first versus last, and physical prototypes to explore mechanical stresses between layers. * Yang:  There's an EDA gap with respect to 3D that requires additional feature enhancements, retooling, and possibly, new startups. * Pol:  If you don't make the move to 3D now, no matter where you are in the supply chain, the "Big Guys" will lock you out. * Radojcic:  There are incremental costs to going 3D, but continued scaling, in combination with 3D technology and the tools/flows needed to manage thermal/mechanical interactions, will produce a "gradual & graceful evolution." When the 3D Panel ended, it was time to rush off yet again, this time to the Wednesday keynote offered by IBM's Bernie Meyerson. To be honest, however, I'd run out of steam. Having heard Meyerson speak repeatedly at DAC, Semicon, etc., over the last few years, I decided to skip it. Instead, I found a quiet corner in an unoccupied conference room to eat lunch and unwind. Perhaps not admirable from a Be-Everywhere/See-Everything point of view, but more cathartic given the rest of Wednesday was consumed with vendor meetings ... * DOCEA:  Based in France, the company released its ACEplorer 2.0 at DATE in April, and announced at DAC in June that ST-Ericsson has adopted the tool, which keeps keeps the power model separate from the performance model, per Ridha Hamza. * PolyTEDA: President & CEO Vlad Marchuk and Sales & Marketing VP Brad O'Connell told a lively narrative regarding the company's history. Company founders worked on CAD issues related to chip design in Moscow in the midst of the Cold War. As the world moved beyond that era, the technology relocated to Canada where the company was founded in 1997. O'Connell said PolyTEDA tools are built on a series of algorithms that scale linearly, with design rules written into an executable compiled directly into the design. [Good to see Ravi Ravikumar, formerly at ChipMD, is now at PolyTEDA.] * BEEcube:  Founder & CEO Chen Chang and SVP Joseph Rothman said the company's technology, the Berkeley Emulation Engine, is spun out of U.C. Berkeley. BEE1 & BEE2 were available in academia in 2001 & 2004, respectively, BEEcube was founded in 2006, BEE3 was commercialized in 2007, which "scales single FPGA boards to complex systems with tens to hundreds of FPGAs," and BEE4 will be available by Q3 2010. * Compaan:  Based in The Netherlands, company CEO Bart Kienhuis and CCO John van Brummen said the company focuses on parallelization technologies to improve efficiency and throughput in C code targeted at multi-processor SoCs. The company released the Compaan HotSpot Parallelizer for ISO C in May. * X-FAB: Business Development VP Mark Miller said the company – with fabs in Germany, Malaysia, the UK, and the US – is a "boutique foundry" serving a carefully focused market niche: Mixed-signal, Analog and MEMS, with specialty customers worldwide. Miller offered an excellent tutorial on economics: Foundries are driven by profit and wafer volume, period! * Silicon Frontline:  Delighted to wrap up my last DAC meeting with the tremendously optimistic & energetic VP of Sales Dermott Lynch. The company's technology includes pattern-matching tools, "providing guaranteed accurate 3D extraction and and analysis for IC design." It's for others to determine the efficacy of the company's tools, but it's for me to tell you that Lynch is probably their best "secret sauce." In and around these meetings Wednesday at DAC, I also caught part of the Pavilion Panel, SOC Verification: Are We there Yet?, moderated by Verilab VP JL Gray. The fact that the question's even being asked is a clue as to the answer, although IBM's John Goss, Qualcomm's Rowland Reed, and Nvidia's Dave Whipp still found lots to talk about in front of a sympathetic audience who expressed agitated frustration with the current state-of-the-art in verification tools. Goss captured the mood ... * We need better tools for model checking with consistency! Also on Wednesday afternoon, I ran up to the 2nd floor at one point to catch a few minutes of the highly animated User Track Poster Session & Ice Cream Social taking place in the hallways there. Really great to see so much enthusiasm from the presenters and those interacting with them. UT Co-Chairs Soha Hassoun [Tufts] and Patrick Groeneveld [Magma] worked long and hard to make the 2010 UT Event a huge success, with multiple sessions over 3 days, dozens of participating companies, daily poster sessions, and an excellent closing panel. Next year's UT organizers have a tough act to follow! Unfortunately, short on time Wednesday afternoon, I missed Kathryn Kranen's Pavilion Event – High School Panel: You don't know Jack! However, IBM's John Goss mentioned it while participating on JL Gray's panel during the following hour. Goss commended Kranen's discussion with the high school kids as highly informative: What better way to understand what the customers wants than to hear it directly from those who use today's latest/greatest consumer products? By the end of the afternoon on Wednesday, there was only one last Must Attend Event. I'm clearly the last to discover that for 5 years now, our friends at Forte Design Systems have hosted a Bagpipe Farewell during at the close of the last hour on the last day of the DAC Exhibition Hall. It was fabulous, with hundreds on hand at the Forte Booth to bid adieu to the #47DAC Show floor, while also hoping to win one of several prizes raffled off by the ever-affable Brett Cline, Forte VP of Sales & Marketing. And so closed the commercial side of #47DAC, and with it arrived the moment to ask ... How did it go for the exhibitors? The answer was, apparently well. Because, no matter who I spoke to, in Anaheim or in these several weeks since DAC ended, the decision has seemed unanimous: DAC 2010 was far, far better than DAC 2009, a 180-degree about face compared with #46DAC in San Francisco. It's true, many reported there were visibly fewer attendees in Anaheim, but those who did come were the real thing – Real Customers. Real Decision Makers. Real Stakeholders. The Real Thing.  I didn't speak to a single exhibitor, on the record or off, that wasn't pleased with the quality of the traffic they enjoyed at #47DAC. That's great news for everybody involved! ************************************ Thursday: June 16th ... Which brings us to Thursday at DAC, a less intense, but very well-attended set of sessions that lasted all the way to 6:01 PM in Anaheim. My schedule included moderating the first of three 2-hour sessions that comprised ... * Embedded/SOC Enablement Day Speakers in my session included Intel VP & General Manager Gadi Singer, who gave a detailed 40-minute keynote, ATIC's Walter Ng, Cadence's John Bruggeman, and Virage Logic's Yervant Zorian, who also served as Organizer of the the day-long Special Track. [Note that Virage Logic is in the process of being acquired by Synopsys.] The speakers were excellent, and the audience fully engaged. Here are some highlights ... * Gadi Singer: Intel needs EDA to take a systems view of design, supporting rapid prototyping better hardware/software integration, and automated tools and flows to connect pre- & post-silicon. * Walter Ng: Displayed a Periodic Table to illustrate the deep knowledge of physics & material science required for the foundries to scale to each additional node. He said it's a myth that IDMs beat foundry/fabless/EDA/IP collaborations to market, even at next gen nodes. * Yervant Zorian: Industry's rush to disaggregation is facilitated by access to robust IP. Better collaboration with foundries will produce better yield learning, device characterization, optimization, and improvement. * John Bruggeman: By 2015, OEMs will hand the model to the fabs, who'll design, verify, and manufacture the system. Plus Android looms & may kill the semiconductor industry by commoditizing silicon. EDA's got to start looking up to the apps part of the supply chain to survive. At the conclusion of the four presentations – distinct, but glummed together by the Goodest of Good Glues – there was supposed to be a panel discussion, but we ran out of time. Besides, we all had to rush down the hall to catch the 11:15 PM Thursday Keynote being given by Motorola VP of Innovation Iqbal Arshad in Ballroom ABC. When I interviewed Arshad earlier this year for an article posted on the DAC.com Knowledge Center, he restricted our conversation to the business aspects of the recently released Motorola Droid Smartphone. During his DAC Thursday Keynote, however, Arshad ran through the "gory geeky details" of the Droid, "a powerful system, difficult to integrate." He said his team didn't have all of the tools needed to do that integration: "There's lots of opportunities there for EDA!" Arshad also said EDA tools for power management are "far from perfection!" Hence, Motorola developed their own proprietary solutions. Overall, per Arshad, "The EDA tools are out of control," with vendors only testing their tools on "their own island" within the design, and oblivious to the larger system. "An SOC isn't a system," he intoned. "It's just a chip!" He added, "Embedded computing is now main stream computing. EDA needs to use software as a strategic advantage – not just for components, but for the system itself!" His critique notwithstanding, Arshad was well received by his audience of many hundreds, a natural in front of an engineering crowd in both manner of speaking and manner of dress. No wonder his business card reads: "Vice President of Innovation." [Note: the keynote was videotaped and will be available soon on the DAC website.] Not everyone in the audience was satisfied, however. I got an earful of criticism from a knowledgeable player in the industry, after Arshad's talk, complaining that the Motorola engineering's not cutting edge and the talk devoid of new or valuable information. Let's see, how does that go? You can please some of the people all of the time, and all of the people some of the time, but ... Lunch followed the Thursday keynote, which was followed by a multitude of afternoon sessions. I was really amazed to see how many people were still on hand in Anaheim to attend all of it – a proof-point as to the quality of the sessions scheduled for the day after the Exhibition Hall closed. I attended part of the second 2-hour session associated with Embedded/SOC Enablement Day. Among the speakers was MontaVista CTO James Ready, who gave a very detailed tutorial about the development of Open Source everything, addressing the "tyranny of the economics of software development." [Note that MontaVista Software was acquired by Cavium Networks in 2009.] Xilinx CTO Ivo Bolsens also spoke, saying FGPAs are fully ready for end-product implementation: "Application-specific processing platforms will offer tighter integration, processing subsystems on FPGA fabric." I also attended part of the hour-long closing session associated with the 2010 User Track. Speakers included folks from Cisco, Broadcom, Intel, IBM, and Infineon. Together they detailed various horror stories in recent design projects. Panel moderator Leon Stok emphasized that this highly candid session was taped, and will be available for viewing soon on the DAC website. [Note also that Stok is set to be General Chair for #48DAC in San Deigo in 2011.] My last 2 hours in the Anaheim Convention Center were spent at the lively, if somewhat less than cordial, panel discussion ... * What Input Language is The Best Choice for High-Level Synthesis? Moderated by the fabulously outspoken Dan Gajski from U.C. Irvine, panelists included a Who's Who of System-level Design Experts ... * Anmol Mathur, Calypto Design Systems * Michael McNamara, Cadence Design Systems * Rishiyur Nikhil, Bluespec * John Sanguinetti, Forte Design Systems * Andres Takach, Mentor Graphics * Devadas Varma, AutoESL Design Technologies Dr. Gajski should have had a whip & chair to control this huge group of combatants as they went at it verbally, attempting to bolster their own positions and discredit adversaries in the room. Instead, Gajski displayed the results of various questions posed to his panelists, pre-panel, including ... * What's the ideal system-level language? * What are the most important language features? * How do we extract HW features from languages? * How can we express parallelizing efficiently? * Can we do synthesis of multi-core platforms? The answers to these and other questions were displayed in endless spreadsheets, which taken together reflect the current fractured thinking on system-level design. Languages invoked included: SystemC, SystemVerilog, C++, and even Specman; Features invoked included: useful for both design & verification, support for concurrency & data types, timing elasticity, modeling at multiple levels of abstraction, code reusability, expression of parallelism, architectural transparency, full language synthesizability, compatibility with C/C++, standards-based, integrated into the tool ecosystem, non-proprietary, and suitable for both software & hardware. Specifics aside, Gajski summarized characteristically: "In Academia, we can imagine anything! The perfect tool in a perfect world would go from C to architecture to implementation!" Over the next 90 minutes, the conversation was complex, cerebral, and contentious – particularly Forte versus Bluespec – and peppered with pithy sound bytes ... * Anmol Mathur: You want a language that's flexible and elastic, but one size does not fit all! * Andres Takach: We shouldn’t just think about languages, we should think about what we’re trying to do! * Rishiyur Nikhil: We're not just inventing new languages because we're language cowboys, [but because] of much deeper issues! * Devadas Varma: We should look at whatever language is best for a particular device. It's time we stopped obsessing about languages! * John Sanguinetti: We're confusing the process here. You don't just take a C algorithm and stick it into HLS, and then say you're done. The job of hardware design isn't being taken over by the high-level synthesis tool! * Michael McNamara: We're trying to capture intent at the highest level of abstraction. The problem is von Neumann is a simplified model of computation, programmed at the level of a single ALU. How do we capture these algorithms on massively parallel machines? [That being said, all 6 panelists said yes (with qualifications), it's possible today with HLS to synthesize multi-core platforms.] HLS was nowhere near settled when, in the final minutes of #47DAC, Tensilica's Grant Martin offered a harsh reality check from the bleachers: "There's crap code being written everywhere. Many users today can't write well in any language!" Global language ambiguities thus confirmed, there was only one unambiguous take-away from Session 49 ... The greatest agitator for cracking The Enigma of HLS Language continues to be Dan Gajski: "We need to get past C, a 40-year-old language that has too much side effect and too little intent!" Clearly, it was well worth the effort to stick around for the closing hours of #47DAC in Anaheim. In the face of a 7-hour drive back to Northern California, I had intended to leave before the HLS session ended, but couldn't tear myself away from this most crucial of panel discussions. Driving north endlessly on 5 under a moonless sky seemed a small price to pay to be there. ************************************ DAC 2010 was full of winners ... The week in Anaheim yielded a number of awards, both in Academia & Industry. Of course, given the energy & optimism evident at DAC 2010, compared with DAC 2009, it's easy to suggest that everyone involved in organizing and running the show in Anaheim in June was a winner ... Good job, guys! * Best Paper: CMU's W.Zhang & X.Li, UIUC's R.Rutenbar: "Bayesian Virtual Probe: Minimizing Variation Characterization Cost for Nanoscale IC Technologies * Best User Track Poster Awards Toshiba: "A New Timing Closure Methodology for an SOC with Multiple On-chip Regulators" Oracle: "Maximizing the Value of Your Formal Run" * ACM Student Research Competition: Graduate Category First Place – Tan Yan, University of Illinois: "A Novel Placement Approach to Length-Matching Routing" Second Place – Peter Milder, Carnegie Mellon University: "A Formula-Driven Approach for Compiling and Optimizing Hardware Implementations of DSP Transforms" Third Place – Xiangyu Dong, Penn State University: "Modeling and Leveraging Emerging Non-Volatile Memories for Future Computer Designs" * ACM Student Research Competition: Undergraduate Category First Place – Tsung Wei Huang, National Cheng Kung University, Taiwan: "Droplet Routing Algorithms for Digital Microfluidic Biochips" * EDA360 Idol Contest – EVE's Luc Burgun [See his performance] ************************************ Losers & MIA in Anaheim ... There were a significant number of Friends & Colleagues – The Good Glues – who were no-shows in Anaheim this year. It's not appropriate to name them by name, but you know who you are. Please be assured that you were missed, because the EDA Ecosystem was diminished by your absence. Hope to see all of you next year in San Diego! As far as Losers at DAC are concerned, there's only one category in my book ... There wasn't enough time to attend what looked to be numerous superb sessions in Anaheim. Hopefully, next year these same topics will pick up where they left off ... * Advanced Clock Design & Flip-chip Layout * Interconnect Networks: Present & Future * Engineering Biology: Fundamentals & Applications * A Decade of NOC Research: Where do we stand? * IC Design: Future in the Clouds? * What's Cool in Ultra-Low-Power Design? And, the over-arching tutorial that everyone at DAC should have attended? * How to Write Better Software! ___________________________________________________________ Peggy Aycinena owns and operates EDA Confidential: www.aycinena.com Copyright (c) 2010, Peggy Aycinena. All rights reserved.